The present invention relates to an integrated circuit, and more particularly to a memory integrated circuit of so-called CMOS type where different channel types of insulated-gate field-effect transistors are employed.
CMOS circuits have been widely used because of their low power consumption, in which P type and N type field effect transistors are employed. In general, a CMOS circuit arrangement is formed on a semiconductor substrate of a first conductivity type provided with well regions of a second conductivity type opposite to the first conductivity formed therein in order to arrange both of P and N channel transistors on the same semiconductor chip. In this arrangement, it is required to provide the substrate and the well region with ohmic contacts for potential sources (V.sub.CC potential and V.sub.SS potential).
In the CMOS circuit, however, as is well known, a current triggered by an external noise voltage or the like flows through the substrate or the well region, and a voltage drop due to this current acts as a dominant factor deciding the degree of occurrence of a parasitic thyristor effect, that is, a so-called latch-up phenomenon caused in the CMOS structure. Accordingly, methods for preventing occurrence of this latch-up phenomenon have been performed such that a part of the well region or the substrate is made of low resistance layer by increasing the impurity concentration thereof, or the supplying of potential for the well region or the substrate is effected by performing the connection with a metal having a low sheet-resistance such as aluminium with a width as large as possible in layout.
However, with the recent increases in the memory capacity and in the density of the semiconductor memory circuit arrangement, it has been required to employ a fine patterning technique and/or bi-layer or stacked layers of polycrystalline silicon structure and the like. The above situation is the same for the CMOS memory circuit arrangement also, and particularly according to the layout of the group of memory cells, an extensive variation of chip size is caused. That is, although the mask pattern used for fabricating the circuit arrangement is subject to the fine patterning, the contact area between a power source wiring and the well region or the substrate cannot be simply reduced in view of the latch-up phenomenon. In addition, in the situation where the bi-layer polycrystalline silicon structure, for instance, the upper polycrystalline silicon layer containing N type impurities is used for a wiring for supplying the V.sub.SS power source, the direct ohmic electrical connection to a well region of a P-type or a substrate of a P-type is impossible, so that it is necessary that once the N doped polycrystalline silicon is connected with a metal such as aluminum, and further the metal is connected with the P type well or the P type substrate. As a result, although the bilayer polycrystalline silicon structure is incorporated for the purpose of effecting the high density of integration, the expected high density cannot be attained in a specified pattern, for instance, a group of memory cells because of the above mentioned indirect connection between the power source wiring and the well region or the substrate.